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AXI Write Address Changes While Stalled

MediumWaveform DebuggingSystemVerilog

Each column is one rising clock edge. AWVALID and AWADDR are driven by the source, while AWREADY is driven by the receiver. Rule to apply: While AWVALID=1 and AWREADY=0, AWVALID must remain high and AWADDR must remain unchanged until the address handshake. Which channel stability assertion fails first?

Waveform for AXI Write Address Changes While Stalled. Signals: AWVALID, AWREADY, AWADDR. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. AWADDR must remain stable while AWVALID is high and AWREADY is low.
  2. B. AWREADY must be high before AWVALID rises.
  3. C. AWVALID must be a one-cycle pulse.
  4. D. AWADDR must become zero after a handshake.
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