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Hardware interview practice

Verify a return-stack trace validator

MediumUVM ComponentsSystemVerilog

Write the format and stack oracle for a validator fed by two independent Universal Verification Methodology (UVM) stream agents, one for push traces and one for pop traces. Equal transaction IDs identify the pair.

Reviewed example

Work through one case

Input
id7 push frame=[A,B,C]; id7 pop frame=[C,B,A], with either half allowed to arrive first
Expected output
format_error=0; sequence_valid=1; first_bad_index=0

Both halves have equal unique value sets, and simulating the stack reproduces every pop in order.

What to cover

Requirements

  1. Accept two already assembled 1-to-16-value queues belonging to the same ID and predict format_error for overlength, unequal lengths, duplicate values, or unequal value sets.
  2. For a well-formed pair, simulate a stack and return sequence_valid or the first impossible pop index.
  3. Perform all format checks before stack simulation so malformed input is not mislabeled as a legal but impossible sequence.
  4. Treat frame assembly, four-ID pairing, missing-mate watchdogs, response matching, and reset epochs as follow-up scoreboard architecture.