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Q078FreeSystemVerilog

Clock-Gating Behavior Checker

Difficulty
Hard
Topic
Clock and Reset
Language
SV
Interview prompt

Question

Verify that a gated clock emits complete pulses only when functional enable or scan bypass is active. The monitor receives ordered edge callbacks from the reference and gated clocks.

Starting point

Question code

class ClockGateChecker;
  void on_ref_posedge(bit enable, bit scan_enable);
  void on_ref_negedge(bit enable, bit scan_enable);
  void on_gated_posedge();
  void on_gated_negedge();
  int error_count();
endclass
Reviewed example

Trace one case

Input
cycle 0: enable=0
cycle 1: enable rises while source clock is low
cycles 2-3: enable=1
cycle 4: enable falls while source clock is low
Expected output
gated clock emits complete pulses only during cycles 2-3; no runt pulse at either boundary

Latching the enable in the safe clock phase prevents a mid-pulse gate transition.

What to cover

Requirements

  1. Produce exactly one gated pulse for every enabled reference-clock cycle.
  2. Reject extra gated edges while both enables are low.
  3. Require each gated rising edge to be paired with a falling edge before the next pulse.
  4. Flag enable changes during the unsafe reference-clock phase under the stated latch model.
Continue practicing
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