Q118FreeSystemVerilog
Clock-Gating Behavior Checker
Question
Verify that a gated clock emits complete pulses only when functional enable or scan bypass is active. The monitor receives ordered edge callbacks from the reference and gated clocks. Use a low-level transparent enable latch and positive reference high/low intervals. Start observation at a reference rising edge while the gated clock is low. Invoke each reference callback before any coincident gated callback at the actual edge timestamp, with no monitoring delay. The supplied package uses 1 ns units and 1 ps precision. Every gated rising/falling edge must coincide with the corresponding reference rising/falling edge; count and pair edges as well. Enable inputs may change during the low phase; assume no unobserved high-phase glitches between callbacks.
Implementation scaffold
package clock_gate_checker_pkg;
timeunit 1ns; timeprecision 1ps;
class ClockGateChecker;
bit expected_this_cycle, have_cycle, reference_high;
realtime last_ref_rise, last_ref_fall;
bit high_phase_enable, high_phase_scan;
int unsigned gated_rises, gated_falls, errors;
function void fail(string message);
errors++;
$error("clock-gate checker: %s", message);
endfunction
// Call the reference edge callback before a coincident gated edge callback.
function void on_ref_posedge(bit enable, bit scan_enable);
// TODO: implement the stated callback behavior.
endfunction
function void on_ref_negedge(bit enable, bit scan_enable);
// TODO: implement the stated callback behavior.
endfunction
function void on_gated_posedge();
// TODO: implement the stated callback behavior.
endfunction
function void on_gated_negedge();
// TODO: implement the stated callback behavior.
endfunction
function int error_count(); return errors; endfunction
endclass
endpackageTrace one case
At reference rising edges 0,1,2,3,4, the combined enable is 0,0,1,1,0. It changes only during preceding low phases. Reference callbacks occur before coincident gated callbacks.One complete gated pulse in cycles 2 and 3; no gated edges in cycles 0,1,4.The value at the end of each transparent low phase determines whether the following complete high pulse is emitted.
Requirements
- Produce exactly one gated pulse for every enabled reference-clock cycle.
- Reject extra gated edges while both enables are low.
- Require each gated rising edge to be paired with a falling edge before the next pulse.
- Flag enable changes during the unsafe reference-clock phase under the stated latch model.