Question 01MediumRTL Design
How to Build a Synchronous FIFO in SystemVerilog
Design a parameterized synchronous FIFO, then write a small bus-functional model that can reset it, push one item, and pop one item without testbench races. W and DEPTH are positive integers; leave PW and CW at their derived defaults. One caller owns each BFM instance and serializes its reset, push and pop calls.
Concise answerModel occupancy from accepted reads and writes, not raw requests. Permit a write at full only when a read also succeeds, register the popped word, update count from the push/pop combination, and wrap pointers explicitly at DEPTH - 1. In the BFM, use a clocking block and sample registered read data on the following edge.
Question 02MediumClock Domain Crossing
Clock-Domain Crossing Strategies for ASIC Interviews
Choose the correct clock-domain crossing (CDC) method for four signal types: a stable one-bit level, a short pulse, a held multi-bit setting, and a continuous stream. Then implement the one-bit level and pulse crossings. Raw reset drives the reset-release chains; their local synchronized outputs drive the corresponding functional reset pins. Reset cancels an event in flight. Physical integration must check synchronizer placement, reset pulse width, reset-tree recovery/removal and CDC timing; digital simulation does not establish those physical guarantees.
Concise answerUse a two-flop synchronizer for a stable one-bit level; convert a short pulse into a source toggle and acknowledge it before accepting another event. Hold multi-bit control data stable under a bundled-data handshake, and carry continuous traffic through an asynchronous FIFO. Each destination domain also needs its own reset-release synchronization.
Question 03EasyReset Design
Async Assert, Sync Deassert Reset
Design an active-low reset conditioner with asynchronous assertion and a two-flop synchronized release. In ideal RTL, release follows two destination-clock edges after arst_n rises; physical synchronization can add uncertainty near a sampling aperture. Explain when synchronous and asynchronous reset styles are appropriate.
Concise answerClear both stages of a two-flop chain asynchronously when arst_n falls. After arst_n rises, shift a 1 through the chain on destination-clock edges and derive srst_n from the second stage. Instantiate this conditioner separately for every unrelated clock, and reset only state that the design contract requires.
Question 04HardRTL Design
How a Ready/Valid Skid Buffer Handles Backpressure
Design a two-entry ready/valid skid buffer that can accept one extra item after downstream stalls, keeps output data stable while stalled, and removes the combinational ready path from downstream to upstream. Assume a positive static data width W and the usual sender rule: hold valid and payload until accepted. Transfers and stall obligations apply on rising edges outside reset. Active-low asynchronous reset discards all buffered items; release it safely for this clock before traffic resumes.
Concise answerImplement the buffer as a two-entry FIFO with registered occupancy. Set upstream ready whenever occupancy is below two, output the head entry whenever occupancy is nonzero, and update storage from the four push/pop combinations. A stalled output keeps its head value unchanged; a full buffer may insert one bubble because ready cannot anticipate a same-edge pop.
Question 05EasyUVM Components
How to Pass a Virtual Interface with uvm_config_db
A top-level module must make one virtual bus_if available to both an agent's driver and monitor. Which pattern is most idiomatic?
Concise answerPublish the concrete interface handle through `uvm_config_db#(virtual bus_if)` using a scope that covers the agent’s driver and monitor, then retrieve it during each component’s build phase. The UVM factory cannot create an HDL interface instance.
Question 06EasyUVM Components
uvm_object vs. uvm_component
A reusable packet configuration has no hierarchy, ports, or phase behavior. Why is extending uvm_object usually preferable to extending uvm_component?
Concise answerUse `uvm_object` because the configuration is data rather than a structural testbench element. It needs neither a hierarchical parent nor phase callbacks, ports, or persistent component lifetime. Choosing an object keeps construction and reuse simpler without preventing factory registration or randomization.
Question 07EasyUVM Components
UVM get_next_item and item_done Handshake
What is wrong with this driver loop?
Concise answerThe loop requests a second item before completing the first. After each successful `get_next_item(req)`, the driver must finish driving that request and call `item_done()` exactly once before another `get_next_item`. Otherwise the sequencer-driver handshake can stall or report a protocol violation.
Question 08EasyUVM Components
How a UVM Analysis Port Works
Which statement best describes uvm_analysis_port::write?
Concise answer`uvm_analysis_port::write` distributes one transaction handle to every connected subscriber without a return handshake. It is a function-based observation broadcast, permits zero subscribers, performs no arbitration, and does not automatically clone the transaction for each recipient.
Question 09MediumReference Models
How to Build an Out-of-Order UVM Scoreboard
A DUT can return responses out of order and may reuse transaction IDs after reset. Which scoreboard design handles matching and reset most robustly? A response generation must be carried by the interface or established by a documented freshness guarantee; assigning the current local epoch to every arriving response is not such a guarantee.
Concise answerUse identity-based matching keyed by transaction ID plus a reset generation, and define what reset does to outstanding expectations. This supports out-of-order completion while preventing a post-reset response from matching stale pre-reset state that happened to use the same ID.
