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Q163FreeSystemVerilog

Eight-bit scan-chain RTL

Difficulty
Medium
Topic
DFT
Language
SV
Interview prompt

Question

An eight-flop register supports functional parallel capture and serial scan shifting. Implement the scan behavior with a defined shift direction, reset, and observable serial output.

Candidate starting point

Implementation scaffold

module scan_register_8 (
  input logic clk, rst_n, scan_en, scan_in,
  input logic [7:0] func_d,
  output logic [7:0] q,
  output logic scan_out
);
  always_comb begin : serial_output
    // TODO: Drive the current serial output bit.
  end
  always_ff @(posedge clk) begin : capture_or_shift
    // TODO: Apply synchronous reset, otherwise select serial shift or parallel capture.
  end
endmodule
Reviewed example

Trace one case

Input
Before scan edge: q=8'hA5, scan_en=1, scan_in=0
Expected output
Before edge scan_out=1; after edge q=8'h4A

Old q[7] is observed at scan_out, while the remaining bits shift toward bit 7 and zero enters bit 0.

What to cover

Requirements

  1. With scan_en=1, load q[0] from scan_in and q[i] from prior q[i-1] for i=1 through 7.
  2. Define scan_out as current q[7], making the pre-edge shifted-out bit observable.
  3. With scan_en=0, capture func_d into all eight bits in parallel.
  4. Use synchronous active-low reset; rst_n=0 on a rising edge clears q regardless of scan_en.
Continue practicing
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