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Q136FreeDesign Verification

Plan verification for an asynchronous FIFO

Difficulty
Medium
Topic
CDC Verification
Language
SV
Interview prompt

Question

Create a verification plan for an eight-entry asynchronous FIFO. The clocks are unrelated, and full and empty may update after the synchronization latency allowed by the specification. For this exercise reset is a coordinated flush: one common logical reset asserts both domain reset pins together before traffic, and each release is synchronized locally. Configure the read monitor for the documented memory mode: first-word-fall-through data is sampled before the accepted read edge; registered-read data is captured at its documented response latency. Do not infer read timing from the pointer implementation.

What to cover

Requirements

  1. Exercise assertion and release of reset in both domains, including reset while data is stored.
  2. Sweep clock ratios, relative phase, and drifting phase.
  3. Model only accepted writes and reads, and compare read data in order.
  4. Cover empty/full boundaries, pointer wrap, simultaneous activity, overflow attempts, and underflow attempts.
Continue practicing
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