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asic.fyi

Hardware interview practice

Plan verification for an asynchronous FIFO

MediumCDC VerificationSystemVerilog

Create a concise verification plan for an eight-entry asynchronous FIFO with independent clocks and specification-defined synchronization latency on full and empty.

Starting point

Question code

wr_clk, wr_rst_n, wr_en, wr_data, full
rd_clk, rd_rst_n, rd_en, rd_data, empty
Reviewed example

Work through one case

Input
wr_clk runs 3x faster than rd_clk with randomized relative phase and sustained legal traffic
Expected output
Every accepted read matches the oldest accepted write; no loss, duplication, or reordering occurs

The scoreboard uses acceptance conditions in each domain rather than attempted operations, so permitted flag-synchronization latency does not create false failures.

What to cover

Requirements

  1. Exercise assertion and release of reset in both domains, including reset while data is stored.
  2. Sweep clock ratios, relative phase, and drifting phase.
  3. Model only accepted writes and reads, and compare read data in order.
  4. Cover empty/full boundaries, pointer wrap, simultaneous activity, overflow attempts, and underflow attempts.
Continue practicing
Clock Domain CrossingImplement asynchronous FIFO full and empty logicClock Domain CrossingMatch each signal type to a CDC techniqueReference ModelsScoreboard a maximum-interval accelerator