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Hardware interview practice

Read Returns Data From the Wrong Register

EasyWaveform DebuggingSystemVerilog

Each column is one rising clock edge. A read of address 0x14 is accepted at C2; expected_data is 0x55, but actual_data is 0xAA. Rule to apply: The response mux is selected by the internal one-hot signal reg_sel. reg_sel[1] selects address 0x14 and data 0x55; reg_sel[0] selects address 0x10 and data 0xAA. Which signal should be traced next to test for an address-decode error?

Waveform for Read Returns Data From the Wrong Register. Signals: rd_valid, rd_ready, rd_addr, rsp_valid, expected_data, actual_data. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. The write byte enables.
  2. B. The FIFO occupancy.
  3. C. The one-hot reg_sel decode at C2.
  4. D. The interrupt clear pulse.