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Second Synchronizer Stage Changes Too Soon

MediumWaveform DebuggingSystemVerilog

async_in enters a destination clock domain through two flops. sync1 is the first stage and sync2 is the second stage. Each column is a destination rising edge. Rule to apply: With nonblocking sequential updates, sync2 at an edge receives the previous edge's sync1 value. Therefore a new stable level must appear in sync1 before it can appear in sync2 on a later edge. What is the most direct root cause suggested by the waveform?

Waveform for Second Synchronizer Stage Changes Too Soon. Signals: async_in, sync1, sync2. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. Two-flop synchronizers require sync1 and sync2 to toggle together.
  2. B. async_in must remain low forever.
  3. C. sync1 should change one edge after sync2.
  4. D. sync2 is bypassing the intended one-edge separation from sync1.
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