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Q040FreeDesign Verification

Second Synchronizer Stage Changes Too Soon

Difficulty
Medium
Topic
Waveform Debugging
Language
SV
Interview prompt

Question

async_in crosses into a destination clock domain through two flops, sync1 followed by sync2. Each column shows a destination rising edge. With nonblocking sequential updates, sync2 receives the previous edge's sync1 value. A new stable level must therefore appear in sync1 before reaching sync2 on a later edge. What root cause does the waveform most directly suggest?

Waveform for Second Synchronizer Stage Changes Too Soon. Signals: async_in, sync1, sync2. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. Two-flop synchronizers require sync1 and sync2 to toggle together.
  2. B. async_in must remain low forever.
  3. C. sync1 should change one edge after sync2.
  4. D. sync2 is bypassing the intended one-edge separation from sync1.
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