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Q019FreeDesign Verification

Pipeline Returns the Wrong Tag

Difficulty
Medium
Topic
Waveform Debugging
Language
SV
Interview prompt

Question

Each column shows one rising clock edge. The three-stage pipeline accepts a tag when in_valid=1. Exactly three edges later, out_valid must be 1 and out_tag must match that accepted in_tag. Which fixed-latency pipeline assertion fails at C4?

Waveform for Pipeline Returns the Wrong Tag. Signals: in_valid, in_tag, out_valid, out_tag. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. out_valid must rise one edge after every in_valid input.
  2. B. out_valid must remain high until another input tag arrives.
  3. C. An output three edges later must carry the tag accepted with the matching input.
  4. D. out_tag may change only when in_valid is high on the same edge.
Continue practicing
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