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Hardware interview practice

Pipeline Returns the Wrong Tag

MediumWaveform DebuggingSystemVerilog

Each column is one rising clock edge. A tag is accepted when in_valid=1, and the three-stage pipeline produces its result exactly three edges later. Rule to apply: For every accepted input, out_valid must be 1 exactly three edges later and out_tag must equal the in_tag accepted three edges earlier. Which fixed-latency pipeline assertion fails at C4?

Waveform for Pipeline Returns the Wrong Tag. Signals: in_valid, in_tag, out_valid, out_tag. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. out_valid must rise one edge after every in_valid input.
  2. B. out_valid must remain high until another input tag arrives.
  3. C. An output three edges later must carry the tag accepted with the matching input.
  4. D. out_tag may change only when in_valid is high on the same edge.