UVM interview preparation

Universal Verification Methodology

Refresh the UVM concepts, SystemVerilog patterns, and verification reasoning you need before a design verification interview. Pair transaction-level checking with SystemVerilog Assertions (SVA) when cycle-level interface rules matter.

Question directory

Start from the interview question

Choose a question first. Each link opens its chapter and authored answer.

Testbench architectureWhat is the difference between uvm_component and uvm_object?Architecture + lifecycle
Testbench architectureWhat belongs in a UVM agent, and what changes in passive mode?Architecture + lifecycle
Testbench architectureWhy is UVM a methodology rather than only a class library?Architecture + lifecycle
Phasing and end of testHow does UVM phasing work, and why is it necessary?Architecture + lifecycle
Phasing and end of testWhen should you use run_phase versus the twelve run-time subphases?Architecture + lifecycle
Phasing and end of testHow do objections control when a UVM test ends?Architecture + lifecycle
Factory and configurationWhat problem does the UVM factory solve?Factory + stimulus
Factory and configurationHow would you replace a default driver with an error-injecting driver?Factory + stimulus
Factory and configurationHow is uvm_config_db different from a direct hierarchical reference?Factory + stimulus
Factory and configurationWhat do uvm_component_utils and uvm_object_utils actually do?Factory + stimulus
Sequences and driversHow do a sequence item, sequence, and sequencer differ?Factory + stimulus
Sequences and driversWhat is the exact sequence-driver handshake?Factory + stimulus
Sequences and driversWhat is a virtual sequence, and when is it useful?Factory + stimulus
Sequences and driversWhat are m_sequencer and p_sequencer?Factory + stimulus
TLM and checking pathsHow does an analysis port differ from put or get TLM interfaces?Checking + debug
TLM and checking pathsTrace one transaction from a sequence to a scoreboard.Checking + debug
Reports, debug, and RALWhat is the difference between UVM_ERROR and UVM_FATAL?Checking + debug
Reports, debug, and RALA UVM test hangs. What do you check first?Checking + debug
Reports, debug, and RALWhat does the UVM Register Abstraction Layer provide?Checking + debug

Find a section

Chapter 1 · Architecture & lifecycle

Know what lives where.

Separate persistent structure from transient data, then explain how an agent packages a protocol without mixing stimulus, observation, and checking.

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Chapter 1 · Architecture & lifecycle

Know when time may pass.

Explain the ordered function phases, the two concurrent run-time schedules, and the objection contract that decides when a time-consuming phase may finish.

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Chapter 2 · Factory & stimulus

Swap behavior without rewiring.

Use the factory to replace types at creation time and the configuration database to deliver typed settings by scope, while keeping both mechanisms predictable.

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Chapter 2 · Factory & stimulus

Follow one request end to end.

Trace arbitration, request delivery, pin driving, completion, and multi-interface coordination without confusing sequences, sequencers, items, or drivers.

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Chapter 3 · Checking & debug

Separate actual from expected.

Treat the monitor as the source of observed behavior, use analysis connections for fan-out, and keep prediction independent from the actual-data path.

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Chapter 3 · Checking & debug

Close the loop with evidence.

Choose report severity by recoverability, debug hangs from phase control outward, and use RAL as a synchronized model rather than a magical mirror.

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Practice UVM in the question bank →