Q051FreeSystemVerilog
Measure ready/valid handshake latency
Interview prompt
Question
Track minimum, maximum, total, and average latency from the first valid sample of each transfer through its successful ready/valid handshake. Supply known 0/1 valid and ready samples. One instance observes at most 2^32 - 1 completed transfers, and each pending transfer has at most 2^32 - 1 stalled samples. These bounds keep individual counters and the 64-bit sum representable.
Candidate starting point
Implementation scaffold
class HandshakeLatency;
local bit active;
local int unsigned stalled_cycles;
local int unsigned completed;
local int unsigned min_delay;
local int unsigned max_delay;
local longint unsigned total_delay;
function new();
active = 0;
stalled_cycles = 0;
completed = 0;
min_delay = 0;
max_delay = 0;
total_delay = 0;
endfunction
function void record_completion(int unsigned delay);
// Implement here: record_completion.
endfunction
function void sample(bit valid, bit ready);
// Implement here: sample.
endfunction
function real average_latency();
// Implement here: average_latency.
endfunction
function int unsigned completed_count(); return completed; endfunction
function int unsigned minimum_latency(); return min_delay; endfunction
function int unsigned maximum_latency(); return max_delay; endfunction
function longint unsigned total_latency(); return total_delay; endfunction
endclassReviewed example
Trace one case
Input
valid rises at cycle 4; ready first overlaps valid at cycle 7Expected output
handshake_latency = 3 cyclesLatency is measured from the first pending-valid cycle through the accepting edge, without resetting while valid is stalled.
What to cover
Requirements
- Define a same-cycle valid-and-ready handshake as zero stalled cycles.
- Update statistics exactly once per successful transfer.
- Initialize minimum latency from the first completed transfer rather than from zero.
- Avoid division by zero and return a real-valued average.
- Do not add failed or incomplete transfers to the latency statistics.
