Q098FreeSystemVerilog

Measure ready/valid handshake latency

Interview prompt

Question

Track minimum, maximum, total, and average latency from the first valid sample of each transfer through its successful ready/valid handshake.

Starting point

class HandshakeLatency;
  function void sample(bit valid, bit ready);
  function real average_latency();
endclass

Reviewed example

Input

valid rises at cycle 4; ready first overlaps valid at cycle 7

Expected output

handshake_latency = 3 cycles

Latency is measured from the first pending-valid cycle through the accepting edge, without resetting while valid is stalled.

What to cover

Define a same-cycle valid-and-ready handshake as zero stalled cycles.
Update statistics exactly once per successful transfer.
Initialize minimum latency from the first completed transfer rather than from zero.
Avoid division by zero and return a real-valued average.
Do not add failed or incomplete transfers to the latency statistics.

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