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Q174FreeSystemVerilog

Order the major digital ASIC development stages

Difficulty
Easy
Topic
RTL Design
Language
SV
Interview prompt

Question

A team starts with an approved product specification and ends with validated silicon. Which sequence is the most technically correct high-level flow?

Choose one

Answer choices

  1. A. Functional verification -> wafer fabrication -> RTL -> DFT -> architecture; physical signoff is optional when simulation passes.
  2. B. RTL -> tapeout -> synthesis -> timing signoff -> architecture -> post-silicon validation.
  3. C. Floorplan/place/route -> write the specification -> RTL -> tapeout -> functional verification -> synthesis.
  4. D. Architecture -> RTL plus lint/CDC/RDC -> functional verification -> synthesis/DFT -> floorplan/place/CTS/route -> timing/power/physical signoff -> tapeout -> bring-up and post-silicon validation.
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