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ASIC.FYI

Q097FreeDesign Verification

Monitor ready/valid without SVA

Difficulty
Medium
Topic
Temporal Checks
Language
SV
Interview prompt

Question

Implement a cycle-sampled ready/valid monitor without SystemVerilog Assertions. Detect when valid drops before a handshake and when a continuously asserted valid waits more than a configured number of cycles for ready.

Starting point

Question code

class ReadyValidMonitor;
  function new(int stall_threshold);
  function void sample(bit valid, bit ready);
  function int error_count();
endclass
Reviewed example

Trace one case

Input
cycle 0: valid=1, ready=0
cycle 1: valid=1, ready=0
cycle 2: valid=1, ready=1
Expected output
No transfer on cycles 0-1; one transfer on cycle 2; no protocol error.

The procedural monitor requires valid to stay asserted during the stall, counts only valid-without-ready cycles toward the timeout, and completes on valid && ready.

What to cover

Requirements

  1. Treat valid and ready high in the same sample as one completed transfer.
  2. Once a stalled transfer starts, require valid to remain asserted until handshake.
  3. Count only valid-without-ready cycles toward the stall limit.
  4. Report a prolonged stall once per transfer rather than once per subsequent cycle.
  5. Expose the cumulative error count.
Continue practicing
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