Q140FreeDesign Verification
Monitor ready/valid without SVA
Interview prompt
Question
Implement a cycle-sampled ready/valid monitor without SystemVerilog Assertions. Detect when valid drops before a handshake and when a continuously asserted valid waits more than a configured number of cycles for ready. Supply known 0/1 valid and ready samples. The threshold is 0 through 2^31 - 1. Cumulative error reports in one instance remain at most 2^31 - 1.
Candidate starting point
Implementation scaffold
class ReadyValidMonitor;
local bit waiting;
local bit timeout_reported;
local longint unsigned wait_cycles;
local int stall_threshold;
local int errors;
function new(int stall_threshold);
if (stall_threshold < 0) $fatal(1, "threshold must be nonnegative");
this.stall_threshold = stall_threshold;
waiting = 0;
timeout_reported = 0;
wait_cycles = 0;
errors = 0;
endfunction
function void clear_transfer();
// Implement here: clear_transfer.
endfunction
function void check_timeout();
// Implement here: check_timeout.
endfunction
function void sample(bit valid, bit ready);
// Implement here: sample.
endfunction
function int error_count();
return errors;
endfunction
endclassReviewed example
Trace one case
Input
stall_threshold=2
cycle 0: valid=1, ready=0
cycle 1: valid=1, ready=0
cycle 2: valid=1, ready=1Expected output
No transfer on cycles 0-1; one transfer on cycle 2; no protocol error.The procedural monitor requires valid to stay asserted during the stall, counts only valid-without-ready cycles toward the timeout, and completes on valid && ready.
What to cover
Requirements
- Treat valid and ready high in the same sample as one completed transfer.
- Once a stalled transfer starts, require valid to remain asserted until handshake.
- Count only valid-without-ready cycles toward the stall limit.
- Report a prolonged stall once per transfer rather than once per subsequent cycle.
- Expose the cumulative error count.