RTL design concept refreshers

Question 1

What distinguishes combinational from sequential hardware?

Accepted Answer

Combinational outputs are functions of current inputs. Sequential hardware contains state that is sampled on a defined event, usually a clock edge, so behavior also depends on history. Combinational paths have no intentional memory and must assign every output on every path. Sequential paths include registers, an explicit sampling edge, and a defined policy for reset, enable, and simultaneous events. Describe the inferred circuit first. Coding constructs are evidence of intent, not the definition of the hardware. Why interviewers ask: Whether you can translate behavioral language into gates, storage, and cycle-level timing. Common trap: Saying that blocking means combinational and nonblocking means sequential without discussing the process and inferred hardware.

Question 2

How does incomplete assignment infer unintended storage?

Accepted Answer

If a procedural combinational block leaves an output unassigned on any reachable path, that output must retain its previous value. Retention requires storage, so synthesis can infer a latch. Give outputs safe defaults before conditional overrides, or cover every branch explicitly. Use lint to find incomplete assignments and review priority when multiple conditions can be true. A default branch should express real behavior. It should not hide an impossible or unsafe state. Why interviewers ask: Whether you understand why a latch appears instead of memorizing a style rule. Common trap: Adding a casual default that suppresses the warning but changes required behavior.

Question 3

Why use blocking assignments for combinational calculations and nonblocking assignments for registers?

Accepted Answer

Blocking assignments make ordered intermediate calculations within one combinational evaluation clear. Nonblocking assignments schedule register updates together so clocked state observes pre-edge values. Use always_comb with complete blocking assignments for next-value calculations. Use always_ff with nonblocking assignments for state that updates on the same edge. Keep the ownership of each variable unambiguous and avoid mixing styles inside one state-update process. Why interviewers ask: Whether your simulation model matches concurrent hardware behavior at a clock edge. Common trap: Treating the assignment operator alone as proof that a block is combinational or sequential.

Question 4

How should an RTL finite-state machine be structured?

Accepted Answer

Register the current state in a clocked process, compute next state with complete combinational defaults, and define outputs from state or from state plus inputs according to the timing contract. Name states after observable phases of the protocol, not after code locations. State which edge samples every transition condition and what happens when several conditions arrive together. Use assertions for legal transitions, one-hot integrity when applicable, and required progress. Why interviewers ask: Whether the implementation follows a precise temporal contract rather than an ad hoc case statement. Common trap: Leaving next state unassigned, omitting event priority, or assuming reset alone handles every illegal encoding.

Question 5

When should an output be Moore-style or Mealy-style?

Accepted Answer

A Moore-style output depends on registered state, so its logical value follows state updates, although a combinational decode can still glitch. A Mealy-style output also depends on current inputs, which can reduce response latency but adds an input-to-output path. Choose from the interface timing requirement, not from a blanket preference. If a Mealy output crosses a module boundary, account for glitches, timing depth, and input stability. Register an output when downstream logic needs a clean cycle boundary and the added latency is acceptable; state-only decoding is not itself a glitch guarantee. Why interviewers ask: Whether you can trade latency against timing, glitch exposure, and interface clarity. Common trap: Claiming that one style is universally smaller, faster, or safer.

Question 6

How should encoding and illegal-state recovery be chosen?

Accepted Answer

Choose binary, one-hot, Gray, or another encoding from area, decode depth, transition behavior, implementation guidance, and safety goals. Define recovery only to the level the system actually requires. One-hot often simplifies decode at the cost of more state bits, but synthesis results and target technology matter. Illegal-state detection can recover, flag, reset, or fail safe depending on the system contract. Recovery logic needs verification. It should not create an untested transition that hides corruption. Why interviewers ask: Whether you connect encoding to physical implementation and fault behavior. Common trap: Saying one-hot is always fastest or forcing every illegal state directly to idle without considering safety.

Question 7

Which CDC structure fits a level, pulse, or multi-bit payload?

Accepted Answer

Use a destination-domain synchronizer for a persistent single-bit level, a toggle or handshake for events, and a stable-data handshake or asynchronous FIFO for coherent multi-bit transfers. Write down the source and destination clock relationship, event rate, latency budget, and whether loss is allowed. A narrow pulse can disappear between destination edges, so pulse width and event spacing are part of the contract. Synchronizing bus bits independently does not preserve a coherent word. Why interviewers ask: Whether you select a structure from signal semantics instead of applying the same synchronizer everywhere. Common trap: Sending an arbitrary pulse or multi-bit bus through independent two-flop chains.

Question 8

What does a two-flop synchronizer solve, and what does it not solve?

Accepted Answer

A two-flop chain reduces the probability that metastability propagates into destination logic for a single-bit level. It does not eliminate metastability or guarantee event capture, bus coherency, ordering, or reset sequencing. Only the first stage should directly sample the asynchronous signal, and implementation tools should recognize the chain. Mean time between failures depends on clock rates, toggle rate, available settling time, and device parameters. Downstream logic consumes the final stage and must tolerate the synchronizer latency. Why interviewers ask: Whether you understand the probabilistic and deliberately narrow role of the synchronizer. Common trap: Calling the output metastability-free or treating two registers as a complete CDC review.

Question 9

How should reset assertion and release cross clock domains?

Accepted Answer

When immediate assertion is required, reset can assert asynchronously, but each receiving clock domain should release through its own synchronizer so local state leaves reset on controlled edges. Reset policy is domain-specific. A fully synchronous reset can be appropriate when the clock is guaranteed and timing is planned. Synchronize release separately in every domain and constrain or identify the synchronizer stages for implementation tools. Verify recovery and removal timing, reset-domain crossings, and partial-reset interactions. Why interviewers ask: Whether you distinguish reset entry, reset release, clock availability, and implementation timing. Common trap: Presenting asynchronous assertion and synchronous deassertion as a universal rule without stating system assumptions.

Question 10

When does a ready-valid transfer occur?

Accepted Answer

A transfer occurs only on an active clock edge where valid and ready are both asserted. Interface state that accounts for that beat, such as its pointer or occupancy update, should follow that accepted-transfer event. The source may assert valid before ready, and the destination may assert ready before valid. Avoid a module-to-module combinational loop from ready to valid and back unless the interface contract explicitly permits and times it. Separate latency from throughput when explaining pipelining or buffering. Why interviewers ask: Whether all state updates share one unambiguous definition of an accepted beat. Common trap: Advancing data when valid is high even though ready is low.

Question 11

What must remain stable while a ready-valid channel is stalled?

Accepted Answer

Once the source presents valid data and the destination is not ready, the source keeps valid asserted and preserves the payload until a later edge accepts that same beat. The hold obligation carries from one sampled cycle into the next. Assertions should compare the current valid and payload with the previous stalled cycle. A skid buffer can break a long ready path while preserving the pending beat. Why interviewers ask: Whether you reason about backpressure as a temporal obligation rather than a same-cycle expression. Common trap: Allowing the payload to change under valid while ready remains low.

Question 12

How should a FIFO handle simultaneous push and pop at full or empty?

Accepted Answer

Define accepted push and pop events first, then derive pointer and occupancy updates from those events. Simultaneous operations can keep occupancy unchanged, but boundary acceptance depends on the chosen interface contract. Count only accepted operations, not raw requests. Specify whether a pop from full creates space for a same-cycle push and whether a push to empty can bypass to the output. Size pointers for wrap and distinguish full from empty with occupancy, an extra wrap bit, or equivalent logic. Why interviewers ask: Whether your state transitions remain correct at the exact full and empty boundaries. Common trap: Updating count with independent if statements whose priority mishandles simultaneous operations.

Question 13

How do width and signedness affect inferred arithmetic?

Accepted Answer

Operand width and signedness determine extension, comparison, shift, result width, truncation, and overflow behavior. Make those choices explicit before relying on an expression. Extend operands before addition when the carry bit matters. Cast signed and unsigned values deliberately, especially around comparisons and shifts. State whether overflow wraps, saturates, flags an error, or is impossible by contract. Why interviewers ask: Whether the arithmetic is correct in both simulation and synthesized hardware at boundary values. Common trap: Assuming the left-hand destination width automatically protects intermediate results.

Question 14

How do latency, throughput, area, and timing trade off?

Accepted Answer

Pipelining can shorten combinational paths and increase sustainable throughput, but it adds registers, latency, control alignment, and verification obligations. State cycles of latency and accepted items per cycle as separate quantities. Carry valid, metadata, exceptions, and backpressure through the same pipeline contract as the payload. Use synthesis and static timing results to confirm the expected critical path and area cost. Why interviewers ask: Whether you can connect an RTL transformation to measurable implementation consequences. Common trap: Calling a design faster because clock frequency improved while ignoring added latency or reduced acceptance rate.

Question 15

What evidence makes an RTL answer trustworthy?

Accepted Answer

Use complementary evidence: lint for structural defects, simulation for scenarios, assertions for temporal contracts, CDC and reset analysis for boundaries, static timing for implementation, and formal for safety or progress properties when convergence allows. Name the corner cases and simultaneous events each check targets. Assertions should encode stability, legality, ordering, and progress properties that match the interface contract. Review synthesis results to confirm the intended registers, memories, arithmetic structures, and clock enables were inferred. Why interviewers ask: Whether you treat correctness as an evidence plan rather than a claim that the code looks right. Common trap: Listing tools without connecting each one to a specific failure mode.

Decision	Combinational	Sequential
Depends on	Current inputs	Current inputs and stored state
Typical process	`always_comb`	`always_ff`
Classic failure	Incomplete assignment infers a latch	Ambiguous priority or unsafe reset release

Cycle	valid	ready	payload	Result at edge
t0	0	1	none	No transfer
t1	1	0	A	Stall begins
t2	1	0	A	Hold obligation
t3	1	1	A	Transfer A

Question indexAll RTL interview questions.

RTL Logic modelsCombinational and sequential intent

Where the design remembers state

Current inputs determine the result

A clock edge advances state

Reason it through

Reason it through

Reason it through

RTL State and controlFinite-state machines as timing contracts

Join each transition to its sampling edge

Reason it through

Reason it through

Reason it through

RTL Clock boundariesCDC and reset strategy selection

Match the crossing structure to the signal

Reason it through

Reason it through

Reason it through

RTL Transfers and storageReady-valid, backpressure, and FIFO boundaries

A stall creates a hold obligation

Reason it through

Reason it through

Reason it through

RTL Hardware and evidenceSynthesis, timing, and proof

From behavioral contract to signoff evidence

Reason it through

Reason it through

Reason it through

RTL DesignInterview QuestionsYou Should Master

Question indexAll RTL interview questions.

RTL Logic modelsCombinational and sequential intent

Where the design remembers state

What distinguishes combinational from sequential hardware?+

Reason it through

How does incomplete assignment infer unintended storage?+

Reason it through

Why use blocking assignments for combinational calculations and nonblocking assignments for registers?+

Reason it through

RTL State and controlFinite-state machines as timing contracts

Join each transition to its sampling edge

How should an RTL finite-state machine be structured?+

Reason it through

When should an output be Moore-style or Mealy-style?+

Reason it through

How should encoding and illegal-state recovery be chosen?+

Reason it through

RTL Clock boundariesCDC and reset strategy selection

Match the crossing structure to the signal

Which CDC structure fits a level, pulse, or multi-bit payload?+

Reason it through

What does a two-flop synchronizer solve, and what does it not solve?+

Reason it through

How should reset assertion and release cross clock domains?+

Reason it through

RTL Transfers and storageReady-valid, backpressure, and FIFO boundaries

A stall creates a hold obligation

When does a ready-valid transfer occur?+

Reason it through

What must remain stable while a ready-valid channel is stalled?+

Reason it through

How should a FIFO handle simultaneous push and pop at full or empty?+

Reason it through

RTL Hardware and evidenceSynthesis, timing, and proof

From behavioral contract to signoff evidence

How do width and signedness affect inferred arithmetic?+

Reason it through

How do latency, throughput, area, and timing trade off?+

Reason it through

What evidence makes an RTL answer trustworthy?+

Reason it through

Connect RTL to the rest of the stack.