Skip to question
asic.fyi

Hardware interview practice

Unknown Output After Reset

EasyWaveform DebuggingSystemVerilog

Each column is one rising clock edge. reset_n is the top-level active-low reset; both displayed output registers are still unknown on the first edge after release. Rule to apply: The local reset out_reset_n must clear out_valid to 0 and out_data to 0x00. The top-level and local reset paths may differ. Which signal should be traced next to check whether reset reached the output registers?

Waveform for Unknown Output After Reset. Signals: reset_n, out_valid, out_data. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. The write-data bus.
  2. B. The FIFO full flag.
  3. C. The interrupt mask.
  4. D. out_reset_n at the reset pins of the output registers.
Continue practicing
Waveform DebuggingReset Pulse Is Too ShortWaveform DebuggingBlock Remains in ResetUVM ComponentsBuild a reset-responsive nonblocking driver