Skip to question
asic.fyi

Hardware interview practice

Control a request/acknowledge handshake

MediumFSMsSystemVerilog

Design a four-phase controller that accepts start while idle, holds req until ack, drops req, waits for ack to return low, and emits a one-cycle done pulse when ack is sampled. Write a responder bus functional model (BFM) with a configurable delay.

Three-state request-acknowledge controller beside a four-phase waveform for request, acknowledge, and one-cycle done.
Use the state flow and sampled waveform together to define when request holds and when done pulses.
Reviewed example

Work through one case

Input
cycle 0: req=0, ack=0
cycle 1: req=1, ack=0
cycle 2: req=1, ack=1
cycle 3: req=0, ack=1
cycle 4: req=0, ack=0
Expected output
state: IDLE -> WAIT_ACK -> WAIT_REQ_LOW -> IDLE
done pulses once at cycle 2

The controller holds the request phase until acknowledge and does not accept a second transaction until both sides return low.

What to cover

Requirements

  1. Ignore additional start pulses while a transaction is active.
  2. Keep req asserted continuously until ack is sampled.
  3. Pulse done only for the req-and-ack handshake and do not return to idle until ack is low.
  4. Initialize ack low and drive it for exactly one sampled cycle in the BFM.
Continue practicing
Temporal ChecksCheck hold while stalledTemporal ChecksProcedural stall-stability checkerClock Domain CrossingChoose a safe clock-domain crossing strategy