Q015FreeSystemVerilog
Control a request/acknowledge handshake
Interview prompt
Question
Design a four-phase controller that accepts start while idle, holds req until ack, drops req, waits for ack to return low, and emits a one-cycle done pulse when ack is sampled. Write a responder bus functional model (BFM) with a configurable delay. The environment resets the controller before BFM use and serializes acknowledge() calls because they share one ACK driver.
Candidate starting point
Implementation scaffold
module req_ack_controller (
input logic clk,
input logic rst_n,
input logic start,
input logic ack,
output logic req,
output logic done,
output logic busy
);
typedef enum logic [1:0] {IDLE, WAIT_ACK, WAIT_ACK_LOW} state_t;
state_t state_q, state_d;
always_comb begin : next_handshake_state
// TODO: Implement next_handshake_state using the supplied state and interface.
end
assign req = (state_q == WAIT_ACK);
assign busy = (state_q != IDLE);
always_ff @(posedge clk or negedge rst_n) begin : handshake_state
// TODO: Implement handshake_state using the supplied state and interface.
end
endmodule
interface handshake_if (input logic clk);
logic req, ack;
clocking responder_cb @(posedge clk);
default input #1step output #0;
input req;
output ack;
endclocking
modport RESPONDER (clocking responder_cb);
endinterface
class responder_bfm;
virtual handshake_if.RESPONDER vif;
function new(virtual handshake_if.RESPONDER vif); this.vif = vif; endfunction
task acknowledge(input int unsigned delay_cycles = 0);
// TODO: implement this body.
endtask
endclassReviewed example
Trace one case
Input
At C0, sample start=1 while idle. At C1, sample ack=0. At C2, sample ack=1. At C3, ack is still 1. At C4, sample ack=0.Expected output
After C0/C1: req=1, done=0, busy=1. After C2: req=0, done=1, busy=1. After C3: req=0, done=0, busy=1. After C4: idle, with req=done=busy=0.The done register marks one sampled completion. Returning ACK low finishes the four-phase exchange; ACK changes between edges do not directly drive done.
What to cover
Requirements
- Ignore additional start pulses while a transaction is active.
- Keep req asserted continuously until ack is sampled.
- Register done from the sampled req-and-ack handshake. It stays high for the following clock interval only; a between-edge ACK pulse does not create done. Remain busy until ACK is sampled low.
- Initialize ack low and drive it for exactly one sampled cycle in the BFM.