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Q122FreeSystemVerilog

Explain What Static Timing Analysis Proves

Difficulty
Easy
Topic
Timing
Language
SV
Interview prompt

Question

A synchronous ASIC has completed synthesis and has clocks, I/O delays, exceptions, and timing corners defined. Which statement about static timing analysis is correct?

Choose one

Answer choices

  1. A. STA checks only the single longest combinational path and does not analyze minimum delay or hold timing.
  2. B. STA runs every possible functional input sequence and therefore replaces simulation for protocol and state-machine bugs.
  3. C. STA propagates delays through a timing graph without functional input vectors, checks constrained launch-to-capture paths for setup and hold across corners, and depends on complete clocks, uncertainties, I/O constraints, and valid exceptions.
  4. D. An unconstrained path automatically passes because the timing tool has proven that no clock can capture it.
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