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Hardware interview practice

Sequencer locks and grabs

MediumUVM ComponentsSystemVerilog

Sequence A locks a sequencer and then waits for an event that can be generated only after sequence B sends an item on that same sequencer. Why can the test deadlock?

Choose one

Answer choices

  1. A. A lock randomizes B with incompatible constraints
  2. B. A lock prevents B from receiving a grant, so A waits on progress that its own exclusivity blocks
  3. C. lock releases automatically after each item, so B sends too early
  4. D. Locks affect analysis ports, not sequencer arbitration
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UVM ComponentsStart_item and finish_itemUVM ComponentsTiming between start_item and finish_item