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Q091FreeSystemVerilog

Summarize one 32-bit scan-unload mismatch

Difficulty
Easy
Topic
DFT & Physical Design
Language
SV
Interview prompt

Question

A scan diagnostic compares one expected unload word against the observed word and needs both a count and the first failing chain position. Implement the combinational mismatch summarizer.

Candidate starting point

Implementation scaffold

module scan_mismatch (
  input  logic [31:0] expected,
  input  logic [31:0] observed,
  output logic        mismatch,
  output logic [4:0]  first_index,
  output logic [5:0]  mismatch_count
);
  logic [31:0] difference;
  logic        found;
  integer      i;

  always_comb begin : summarize_mismatch
    // TODO: Implement summarize_mismatch.
  end
endmodule
Reviewed example

Trace one case

Input
expected=32'h0000_0000, observed=32'h0000_0028.
Expected output
mismatch=1, first_index=3, mismatch_count=2.

The XOR difference mask has bits 3 and 5 set, so there are two mismatches and bit 3 is the lowest failing position.

What to cover

Requirements

  1. Inputs contain only known bits. Define difference bit i as expected[i] XOR observed[i].
  2. mismatch is 1 if at least one difference bit is set, and mismatch_count is the exact population count from 0 through 32.
  3. When mismatch=1, first_index is the lowest-numbered differing bit; when mismatch=0, first_index is 0.
  4. Use complete combinational RTL with a loop whose bounds are constant and synthesizable.
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