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Hardware interview practice

Interrupt Pulse Is Missing

EasyWaveform DebuggingSystemVerilog

Each column is one rising clock edge. req is a one-cycle interrupt request, and ack is the registered notification returned by the interrupt block. Rule to apply: Every req pulse must produce exactly one ack pulse on the next sampled edge while irq_enable is 1. Which event-response assertion fails on this waveform?

Waveform for Interrupt Pulse Is Missing. Signals: req, ack, irq_enable. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. ack must be high before req.
  2. B. req must stay high until ack arrives.
  3. C. ack must be high on every idle edge.
  4. D. An enabled req pulse must produce ack on the next edge.