Q181FreeSystemVerilog
Bridge a sticky memory-error alarm across clocks
Question
A fast memory-test clock may detect an error while a slower service clock is busy. The alarm must not be lost and only one alarm may be pending. Implement the request/acknowledge alarm bridge in SystemVerilog. The complete module and source/destination state declarations are supplied. src_error and dst_clear are known controls synchronous to their respective local clocks. A supplied reset controller asserts shared rst_n to both domains and releases it only with recovery/removal timing satisfied at every receiving flop in both domains. The integration supplies synchronizer placement and CDC timing constraints; ideal RTL simulation does not establish metastability reliability or physical reset timing. An error sampled while the pre-edge src_pending is high is coalesced, including the edge that clears pending at the end of the handshake. Reset discards an in-flight alarm; new source work begins only after reset release.
Implementation scaffold
// Supplied integration: src_error and dst_clear are known controls synchronous
// to their local clocks. Shared reset assertion clears both domains together;
// the external reset controller meets recovery/removal at every receiving flop
// when releasing rst_n in BOTH domains. Physical synchronizer placement/CDC
// constraints are part of integration, not proved by this ideal RTL simulation.
module sticky_alarm_cdc (
input logic src_clk, dst_clk, rst_n,
input logic src_error, output logic src_pending,
output logic dst_alarm, input logic dst_clear
);
logic req, ack;
logic req_meta, req_sync, ack_meta, ack_sync;
always_ff @(posedge src_clk or negedge rst_n) begin : source_request_and_ack_sync
if (!rst_n) begin
// Implement here: reset the source-owned state and ACK synchronizer.
end else begin
// Implement here: synchronize ACK and retain/coalesce one request
// through the complete four-phase return before releasing src_pending.
end
end
always_ff @(posedge dst_clk or negedge rst_n) begin : destination_alarm_and_req_sync
if (!rst_n) begin
// Implement here: reset the destination-owned state and REQ synchronizer.
end else begin
// Implement here: synchronize REQ, sticky set-over-clear, and hold ACK
// through synchronized request return-to-zero.
end
end
endmodule
Trace one case
Pulse src_error once and leave dst_clear low.req and src_pending stay high, dst_alarm becomes and remains high, and ack stays low.The four-phase request remains pending until the destination explicitly clears the sticky alarm and raises acknowledgement.
Requirements
- Implement internal four-phase req/ack levels. In the source domain, src_error sets req=1 and src_pending=1; later src_error pulses while pending are coalesced into that request.
- Synchronize req through two destination flops. When a new synchronized req=1 is seen with ack=0, set dst_alarm. A dst_clear on that same edge loses to the set. On a later edge with dst_alarm=1, req=1, and dst_clear=1, clear dst_alarm and set ack=1.
- Synchronize ack through two source flops. When synchronized ack becomes 1, lower req but keep src_pending=1. The destination holds ack=1 until synchronized req becomes 0, then lowers ack; only after synchronized ack returns to 0 may the source clear src_pending.
- rst_n asynchronously clears req, ack, both synchronizer chains, src_pending, and dst_alarm. Reset has priority; no combinational path crosses domains, and dst_clear while dst_alarm=0 has no effect.