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Q080FreeSystemVerilog

Order an RTL-to-GDS flow

Difficulty
Easy
Topic
Physical Design
Language
SV
Interview prompt

Question

A digital block proceeds from synthesizable RTL to a tape-out layout with sign-off checks. Which sequence is in the correct dependency order?

Choose one

Answer choices

  1. A. Floorplanning, routing, synthesis, placement, extraction, clock-tree synthesis, then STA.
  2. B. Synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, sign-off STA, then DRC/LVS.
  3. C. Clock-tree synthesis, RTL simulation, floorplanning, synthesis, routing, then placement.
  4. D. Synthesis, DRC/LVS, floorplanning, placement, then clock-tree synthesis and routing.
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