Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Fixed-Priority Arbiter Picks the Wrong Requester

Hardware interview practice

Fixed-Priority Arbiter Picks the Wrong Requester

EasyWaveform DebuggingSystemVerilog

A two-requester arbiter uses fixed priority. Requester 0 has higher priority than requester 1. Grants are combinational values sampled at each edge. Rule to apply: If req0 is 1, grant0 must be 1 and grant1 must be 0. grant1 may be 1 only when req1=1 and req0=0. What is the root cause of the arbitration error at C3?

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Waveform for Fixed-Priority Arbiter Picks the Wrong Requester. Signals: req0, req1, grant0, grant1. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. The arbiter grants requester 1 while higher-priority req0 is still active.
  2. B. The arbiter grants requester 0 when only req0 is active.
  3. C. The arbiter grants requester 1 when only req1 is active.
  4. D. No grant is asserted when neither request is active.
asic.fyi · Learn silicon end to end.info@asic.fyi