Skip to question
asic.fyi
DesignVerificationSystemVerilogFirmwareArchitectureInterviews
asic.fyi/Interview questions/Verify a framed cache-line rotator

Hardware interview practice

Verify a framed cache-line rotator

MediumUVM ComponentsSystemVerilog

Write a frame oracle and core output properties for a streaming cache-line rotator that samples count and right-shift metadata on the first accepted beat.

Try it in the question bankReason first. Then compare.

Keep this exact question selected while you check your answer and review the full solution.

Practice this question →
Reviewed example

Work through one case

Input
first accepted beat declares count=4,right_shift=1; frame data=[A,B,C,D] with correct last marker
Expected output
output beats=[D,A,B,C] with first/last metadata on the proper endpoints

Shift one modulo four rotates the snapshotted legal frame right and every beat is compared only on an output handshake.

What to cover

Requirements

  1. Assemble transactions only from input handshakes and sample count and shift on the first accepted beat.
  2. Predict a right rotation by shift modulo count; count zero produces one all-zero success beat, while legal nonempty frames produce exactly count beats.
  3. Classify every first/last marker and accepted-beat count as bad-first, oversized-count, early-last, or late/extra; malformed input predicts one coded zero beat.
  4. Assert output stability under backpressure and no internal gap when the receiver remains ready.
  5. Treat input draining, transaction admission, reset epochs, and coverage as follow-up monitor/scoreboard design questions.
Continue practicing

Related questions

Reference ModelsBuild a FIFO reference model→Reference ModelsMonitor an independently stalled binary adder→ConstraintsConstrain and cover an ASCII palindrome checker→
asic.fyi · Learn silicon end to end.info@asic.fyi