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Hardware interview practice

Control a link with return credits

MediumComputer ArchitectureSystemVerilog

A sender crosses a latency-heavy link into an eight-entry receiver buffer. One credit represents one free receiver entry. Design the sender credit counter and transfer rule.

Starting point

Question code

input logic clk, rst_n;
input logic tx_valid;
output logic tx_ready;
input logic [31:0] tx_data;
input logic [3:0] credit_return;
output logic credit_error;

initial credits = 8;
maximum receiver entries = 8;
Reviewed example

Work through one case

Input
credits=0, tx_valid=1, credit_return=2
Expected output
accepted=0 on this edge; next credits=2; credit_error=0

tx_ready is based on the pre-edge zero count. Returned credits become usable only after the state update.

What to cover

Requirements

  1. Reset sets credits=8 and credit_error=0; tx_ready uses the pre-edge credit count.
  2. Compute raw=credits+credit_return-(tx_valid&&tx_ready) once per edge.
  3. Store raw only when it is 0 through 8 and credit_return<=8; otherwise hold credits and pulse credit_error.
  4. When credits is zero, accept no transfer on that edge even if credits return simultaneously.
Continue practicing
Computer ArchitectureCheck per-channel link credits