Control a link with return credits

module credit_sender (
  input logic clk, rst_n, tx_valid,
  output logic tx_ready,
  input logic [31:0] tx_data,
  input logic [3:0] credit_return,
  output logic credit_error
);
  logic [3:0] credits;
  logic accepted;
  logic signed [5:0] raw;

  always_comb begin : preedge_transfer_and_credit_sum
    // Implement here: reset-gated ready, accepted transfer and widened raw sum.
  end

  always_ff @(posedge clk) begin : registered_credit_state
    if (!rst_n) begin
      // Implement here: synchronous reset to eight credits and no error.
    end else begin
      // Implement here: validate return/raw, then hold with error or commit once.
    end
  end
  // Supplied serial datapath transfers tx_data when accepted; this module
  // supplies only its credit permission and error accounting.
endmodule