Q001FreeSystemVerilog
SystemVerilog Blocking vs. Nonblocking Assignments
Question
What values are printed by display and strobe, in that order?
Code to inspect
logic a;
initial begin
a = 0;
a <= 1;
$display("D=%0b", a);
$strobe("S=%0b", a);
endAnswer choices
- A. D=0, S=0
- B. D=x, S=1
- C. D=1, S=1
- D. D=0, S=1
Short answer
Choose D: $display prints D=0 and $strobe prints S=1. The blocking assignment changes a immediately, while the nonblocking assignment schedules its update for the NBA region. $display runs before that scheduled update; $strobe reports later, after the new value has taken effect.
Why this reasoning works
At the start of the initial block, the blocking assignment places 0 into a in the current active-region execution. The following <= statement evaluates its right-hand side but defers writing 1. Therefore the immediate $display call still observes the old current value and emits D=0.
Nonblocking updates are committed later in the same simulation time slot, after active-region work. $strobe waits until the postponed region, when those updates are visible and the time slot has settled, so it emits S=1. No simulation time advances; the difference comes entirely from event-region ordering, which is central to race-free modeling in synchronous RTL.
Interview takeaways
- $display sees active-region state
- NBA updates occur later
- $strobe sees settled state
