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Q024FreeDesign Verification

FIFO Returns the Wrong Head Entry

Difficulty
Easy
Topic
Waveform Debugging
Language
SV
Interview prompt

Question

Each column shows one rising clock edge. A legal pop is accepted at C2 while the FIFO head is 0x31. By C3 the live head has advanced to 0x47, but the response to the C2 pop must still return the captured value 0x31. Instead, actual_data at C3 is 0x47. A pop response must use the pre-update rd_ptr and head value from its acceptance edge. Which signal would you trace next to check whether the response addressed the wrong entry?

Eight rising-edge FIFO samples: the live head changes from 0x31 at C2 to 0x47 at C3, where actual_data returns 0x47 for the earlier accepted pop.
The row live_head names current FIFO state. Compare the accepted C2 head with the response shown at C3.
Choose one

Answer choices

  1. A. The write-data bus of an unrelated register.
  2. B. The interrupt enable bit.
  3. C. The APB PREADY signal.
  4. D. The pre-update rd_ptr and memory read address captured for the C2 response.
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