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FIFO Returns the Wrong Head Entry

EasyWaveform DebuggingSystemVerilog

Each column is one rising clock edge. A legal pop is accepted at C2 while the pre-pop FIFO head is 0x31. By C3 the live head has advanced to 0x47, but the response to the C2 pop must still return the captured pre-pop value 0x31. Instead, actual_data at C3 is 0x47. Rule to apply: A pop response must use the pre-update rd_ptr and head value from its acceptance edge, not the live head after the pointer advances. Which signal should be traced next to test whether the wrong entry was addressed?

Waveform for FIFO Returns the Wrong Head Entry. A pop is accepted at C2 while the pre-pop head is 0x31. At C3 the live head has advanced to 0x47, and actual_data incorrectly returns that current value instead of the captured C2 head. Signals: pop, pop_allowed, expected_data, actual_data. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. The write-data bus of an unrelated register.
  2. B. The interrupt enable bit.
  3. C. The APB PREADY signal.
  4. D. The pre-update rd_ptr and memory read address captured for the C2 response.
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