Skip to question and answer
ASIC.FYI

Hardware interview practice

SVA Overlapped vs. Nonoverlapped Implication

MediumTemporal ChecksMultiple choice

For the one-cycle antecedent a, which property is cycle-equivalent to the property shown?

Question code
assert property (@(posedge clk) a |=> b);

Answer choices

  1. A. a |-> b
  2. B. a throughout b
  3. C. a |-> ##2 b
  4. D. a |-> ##1 b

Concise answer

The answer and the key reason

For this one-cycle antecedent, `a |=> b` is cycle-equivalent to `a |-> ##1 b`. Nonoverlapped implication checks the consequent on the sampled edge after `a`; overlapped implication plus an explicit one-cycle delay reaches that same edge.

Deeper explanation

Work through the implementation and tradeoffs

An assertion attempt begins when `a` is true at a rising-edge sample. With `|=>`, evaluation of `b` starts at the next sampling event, so `b` must be true one clock later. The operator describes clocked sequence timing, not a delay measured in simulator time units.

In `a |-> ##1 b`, the overlapped operator places the consequent sequence at the antecedent endpoint, and `##1` advances the actual `b` test by one sampled clock. The two formulations therefore align for the shown Boolean antecedent. Neither `throughout` nor an undelayed overlapped implication expresses that next-cycle requirement. Both use the same property clock.

What to remember

  • `|=>` starts next cycle
  • `|->` starts at the endpoint
  • `##1` adds one sampled clock

Practice the complete prompt

Explain it first, then compare the reviewed solution.

Open this exact question in the practice bank to attempt it, check your reasoning, and access the full member solution.Practice this question

Keep practicing

Temporal ChecksHow SVA disable iff Handles ResetFunctional CoverageSystemVerilog Coverpoint Bins Interview QuestionFunctional CoverageSystemVerilog Cross Coverage Explained