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Hardware interview practice

Verify unique zero-sum triplets

MediumReference ModelsSystemVerilog

Verify an accelerator that streams every unique sorted three-value combination whose widened sum is zero, in strict dictionary order.

Starting point

Question code

interface triplet_if #(int N=12, W=12)(input logic clk);
  logic rst_n, req_valid, req_ready;
  logic [3:0] count;
  logic signed [W-1:0] value[N];
  logic out_valid, out_ready, out_first, out_last, out_empty, out_error;
  logic signed [W-1:0] a, b, c;
endinterface
Reviewed example

Work through one case

Input
values=[-1,0,1,2,-1,-4]
Expected output
beats=(-1,-1,2) first=1 last=0; (-1,0,1) first=0 last=1

Index triples are normalized and deduplicated by values, then the two unique solutions are streamed in dictionary order.

What to cover

Requirements

  1. Enumerate all index triples from an accepted request, sort each value triple, and deduplicate by values rather than indexes.
  2. Sort expected triples by a, then b, then c and check exact first/last markers.
  3. Use one defined special beat for no-solution and another for invalid count, with all zero payload fields.
  4. Block another request until final acceptance, hold stalled fields stable, enforce progress, and cancel on reset.
Continue practicing
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