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AXI Write Response Is Issued Too Early

MediumWaveform DebuggingSystemVerilog

Each column is one rising clock edge. The address handshake occurs at C1; the write-data handshake waits until C4 because WREADY is low earlier. Rule to apply: BVALID may be asserted only after both the write-address handshake and the write-data handshake have occurred. What is wrong at C3?

Waveform for AXI Write Response Is Issued Too Early. Signals: AWVALID, AWREADY, WVALID, WREADY, BVALID. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. The address is accepted before the data.
  2. B. BVALID rises before the write-data handshake.
  3. C. WVALID remains high while WREADY is low.
  4. D. AWREADY is high in idle cycles.
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