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Q129FreeSystemVerilog

Average four accepted samples

Difficulty
Easy
Topic
RTL Design
Language
SV
Interview prompt

Question

A streaming sensor needs the floor of the average of each non-overlapping group of four accepted unsigned samples. Implement synthesizable RTL for the four-sample averager.

Candidate starting point

Implementation scaffold

module average_four (
  input  logic       clk,
  input  logic       rst_n,
  input  logic       in_valid,
  input  logic [7:0] in_data,
  output logic       avg_valid,
  output logic [7:0] avg
);
  logic [9:0] sum;
  logic [1:0] sample_index;

  always_ff @(posedge clk) begin : accept_sample_group
    // TODO: implement the specified sampled reset and sequential behavior.
  end
endmodule
Reviewed example

Trace one case

Input
Accepted samples: 4, 8, 12, 16
Expected output
avg=10 with one avg_valid pulse after sample 16

The 10-bit total is 40, and floor(40/4)=10. Idle cycles between accepted samples do not change the count.

What to cover

Requirements

  1. On each rising edge with rst_n=1 and in_valid=1, accept one sample; cycles with in_valid=0 do not advance the four-sample group. A sampled low reset instead discards the group as specified.
  2. Use enough accumulator bits for four values of 255, and output floor(sum/4) for each non-overlapping group.
  3. Assert avg_valid for exactly the cycle after the edge that accepts the fourth sample; otherwise drive avg_valid=0.
  4. When rst_n=0 at a rising edge, synchronously discard any partial group, set avg_valid=0, and set avg=0.
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