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Hardware interview practice

Average four accepted samples

EasyRTL DesignSystemVerilog

A streaming sensor needs the floor of the average of each non-overlapping group of four accepted unsigned samples. Implement synthesizable RTL for the four-sample averager.

Starting point

Question code

input logic clk, rst_n;
input logic in_valid;
input logic [7:0] in_data;
output logic avg_valid;
output logic [7:0] avg;
Reviewed example

Work through one case

Input
Accepted samples: 4, 8, 12, 16
Expected output
avg=10 with one avg_valid pulse after sample 16

The 10-bit total is 40, and floor(40/4)=10. Idle cycles between accepted samples do not change the count.

What to cover

Requirements

  1. On each rising edge with in_valid=1, accept one sample; cycles with in_valid=0 do not advance the four-sample group.
  2. Use enough accumulator bits for four values of 255, and output floor(sum/4) for each non-overlapping group.
  3. Assert avg_valid for exactly the cycle after the edge that accepts the fourth sample; otherwise drive avg_valid=0.
  4. When rst_n=0 at a rising edge, synchronously discard any partial group, set avg_valid=0, and set avg=0.