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Q086FreeSystemVerilog

Capture a held multi-bit power-state value across clocks

Difficulty
Easy
Topic
CDC & RDC
Language
SV
Interview prompt

Question

A source clock domain changes a four-bit power-state value, asserts request, and promises to hold the value until an acknowledgement returns from the destination. Which destination-side scheme transfers one coherent value without synchronizing the four data bits independently? Assume the physical bundled-data path is constrained and verified to settle at the destination before the synchronized request permits capture. Holding the bus until acknowledgement also prevents a later source update from changing that capture.

Choose one

Answer choices

  1. A. Synchronize each of the four data bits with its own two-flop chain and concatenate the four outputs.
  2. B. Convert only the request to a one-cycle pulse and let the source change the data on the following source edge without waiting for acknowledgement.
  3. C. Synchronize the request, wait for its destination-domain transition, then capture the held data bus and return a synchronized acknowledgement.
  4. D. Sample the asynchronous data bus every destination edge and use whichever value appears twice in a row.
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