Hardware interview practice
Capture a held multi-bit power-state value across clocks
A source clock domain changes a four-bit power-state value, asserts request, and promises to hold the value until an acknowledgement returns from the destination. Which destination-side scheme transfers one coherent value without synchronizing the four data bits independently?
Choose one
Answer choices
- A. Synchronize each of the four data bits with its own two-flop chain and concatenate the four outputs.
- B. Convert only the request to a one-cycle pulse and let the source change the data on the following source edge without waiting for acknowledgement.
- C. Synchronize the request, wait for its destination-domain transition, then capture the held data bus and return a synchronized acknowledgement.
- D. Sample the asynchronous data bus every destination edge and use whichever value appears twice in a row.