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SystemVerilog constraints interview preparation

Everything you need to refresh about constrained random verification: rand and randc, procedural RNGs, inside, dist, arrays, solve ordering, probability, and solver debugging before a design verification interview.

SystemVerilog Randomization contractKnow what the solver promises.

Separate object randomization from procedural randomness, choose rand or randc deliberately, and treat the Boolean result as part of the transaction contract.

Concept model

Randomization is a legal-solution pipeline

01Build the model
  • Fixed statecurrent object values
  • Unknownsactive rand variables
  • Ruleshard + compatible soft
02Intersect every rule
legalblockedsampled
03Return the contract
At least one legal pointrandomize() == 1

One complete assignment is committed.

Empty intersectionrandomize() == 0

No new values should be assumed.

One solve, one shared model.Written order does not turn the constraints into procedural assignments.

Fixed object state and active random variables enter one declarative model. A successful solve assigns one legal point; an empty intersection returns failure.

Strong answer

rand samples a legal value on each successful randomization and may repeat immediately. randc keeps cyclic state so successive calls on the same object visit each value in its legal domain before repeating.

Reason it through

  • Use rand for normal constrained-random stimulus. A repeated value is legal and is not evidence that randomization failed.
  • Use randc for a small, stable scalar or enum domain when no-repeat traversal is itself the requirement.
  • A new object starts a new randc cycle. Tight or changing constraints can exhaust the remaining cyclic choices and make a later solve fail.
rand and randc comparison
ChoiceAcross callsBest useMain risk
randLegal values may repeatGeneral stimulusAssuming every value appears quickly
randcNo repeat within its cycleSmall IDs or enum sweepsState, cost, and constraint exhaustion

SystemVerilog Domains and distributionsShape the legal value space.

Use inside to define legality, dist to bias sampling, and soft defaults or runtime modes to layer scenario intent without hiding conflicts.

Concept model

Legality and probability are different controls

LegalitySelect the allowed set
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
value inside {[2:7], 12}

Membership removes illegal values. It does not assign probability weights to the remaining values.

Probability weightRead the distribution operator
[0:3] := 4

Full weight per value. The range contributes four weighted entries.

[0:3] :/ 4

Weight shared by the range. The total is divided across its values.

Membership chooses which values remain legal. Distribution operators then assign relative weight, with different range semantics for := and :/.

SystemVerilog Relationships and orderingEncode relationships, not procedures.

Reason about equations, implication, inheritance, and solve ordering as one shared solution space rather than a sequence of assignments.

Concept model

Relationships carve one shared solution space

Legal-pair gridImplication removes exactly one Boolean state

A -> Bis false only when the condition is true and its rule is false.

Relationship strengthPick the rule that matches the requirement
A == BAlways equalLegal states: 00, 11
A -> BOne-way conditionLegal states: 00, 01, 11
A <-> BBoth conditions agreeLegal states: 00, 11

All active relationships are solved together.Source order never turns them into assignments.

Equality, implication, and biconditional rules admit different legal pairs. Written order never turns those declarative relationships into assignments.

SystemVerilog Arrays and collectionsConstrain shape before contents.

Build collection constraints in layers: size, per-element domains, cross-element relationships, uniqueness, and width-safe reductions.

Concept model

Array constraints build from shape to aggregate

01 · Shapedata.size() == 6
02 · Element domainforeach (data[i]) data[i] inside {[1:8]}
03 · Cross-element ruleunique {data}
04 · Width-safe aggregatedata.sum() with (int'(item))

Map each contribution at the intended width, then reduce the completed collection.

The solver establishes the index domain, expands foreach rules over those indices, then applies uniqueness and aggregate relationships to the complete collection.

SystemVerilog Solver probabilityCount solutions before predicting traffic.

Explain how legal-pair counts, solve before, weighted ranges, and rare events affect the stimulus distribution and the time required to reach coverage.

Concept model

Solve ordering changes sampling, not legality

Same legal solution setThree SHORT lengths, twelve LONG lengths
kind == SHORT -> length inside {[1:3]};
kind == LONG  -> length inside {[4:15]};
Marginal distributionSample complete pairs

Sample complete legal pairs. LONG owns twelve pairs while SHORT owns three, so LONG is selected four times as often. All fifteen legal pairs remain available.

Both modes preserve the same legal pairs. Default sampling favors values with more compatible partners, while solve before chooses the ordered variable first.

SystemVerilog Patterns and solver debugMake failures small and reproducible.

Use hooks for procedural derivation, write structured collection problems clearly, and isolate an empty solution space without discarding the failing seed.

Concept model

Reconstruct the failure before changing the model

Failure evidenceReconstruct the exact model that returned zero
Seed and identitytest seed · object type · instanceProve you are replaying the same experiment.
Fixed object staterand_mode() · non-rand valuesFrozen values still participate in active rules.
Active modelclass · inherited · inline · modesHard rules intersect; incompatible soft rules yield.
Observed resultrandomize() == 0

The active hard relationships share no assignment.

Progressive isolationChange one thing, then preserve the evidence
  1. 01Confirm failurecheck the return bit
  2. 02Freeze the scenerecord state + modes
  3. 03Reduce the modeldisable one named block
  4. 04Prove the conflictre-enable one block at a time
rand_mode(0) freezes a variable; it does not remove its value from active constraints.A disabled block may reveal the conflict, but the requirement still needs a specification-backed repair.

Preserve the seed, object identity, fixed state, and active modes. Then reduce the model one named block at a time until the empty intersection is explainable.