Preparing questions and your practice workspace.
SystemVerilog constraints interview preparation
Everything you need to refresh about constrained random verification: rand and randc, procedural RNGs, inside, dist, arrays, solve ordering, probability, and solver debugging before a design verification interview. Pair stimulus constraints with SystemVerilog Assertions (SVA) when behavior must also be checked across clock cycles.
The language bench / constraints
rand bit type_a;
rand bit [1:0] val;
constraint c {
type_a -> val == 3;
val <= 3;
}Question directory
Choose a question first. Each link opens the exact chapter and authored answer.