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Reset Pulse Is Too Short

EasyWaveform DebuggingSystemVerilog

reset_n is an active-low synchronous reset. It is sampled only on rising edges where clk_enable=1; clk_enable is 1 on every displayed edge. Rule to apply: When reset_n falls on an enabled edge, it must be sampled low on at least two consecutive enabled edges, including the fall edge as the first one. Which reset-width assertion fails on this waveform?

Waveform for Reset Pulse Is Too Short. Signals: reset_n, state_valid, clk_enable. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. reset_n must be low on at least two consecutive enabled edges, including the fall edge.
  2. B. state_valid must always equal reset_n.
  3. C. reset_n may fall only when state_valid is 0.
  4. D. C3 does not count toward reset width because clk_enable is 0.
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