Skip to question
SystemVerilogDesignVerificationFirmwareArchitectureASIC Interview Questions→
/Interview questions/Reset Pulse Is Too Short

Q143·Free·Design Verification

Reset Pulse Is Too Short

Difficulty
Easy
Topic
Waveform Debugging
Language
SV
Interview prompt

Question

reset_n is an active-low synchronous reset. It is sampled only on rising edges where clk_enable=1; clk_enable is 1 on every displayed edge. Rule to apply: When reset_n falls on an enabled edge, it must be sampled low on at least two consecutive enabled edges, including the fall edge as the first one. Which reset-width assertion fails on this waveform?

Waveform for Reset Pulse Is Too Short. Signals: reset_n, state_valid, clk_enable. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. reset_n must be low on at least two consecutive enabled edges, including the fall edge.
  2. B. state_valid must always equal reset_n.
  3. C. reset_n may fall only when state_valid is 0.
  4. D. C3 does not count toward reset width because clk_enable is 0.
Exact question handoffPractice Q143

Solve it in the question bank, keep your progress, and reveal the reviewed solution when your access allows.

Open in question bank →
Solution accessEach time you open this Solution, one Practice Credit is used; it is not permanently unlocked. Premium Solution content also uses one credit per opening.
Continue learning

Clock Domains and Reset

Review domain provenance, reset ownership, safe release, recovery, removal, and RDC.

  • Waveform Debugging
  • Reset
Clock Domains and Reset →
Continue practicing

Related questions

Q029 · Waveform DebuggingUnknown Output After ResetEasy→Q099 · Waveform DebuggingBlock Remains in ResetEasy→Q1134 · Waveform DebuggingA Reset Replays an Old Toggle RequestMediumP→Q745 · Waveform DebuggingIndependent Reset Releases Create a Permanent False MismatchHardP→Q009 · Reset DesignSynchronize reset release in each clock domainEasy→
ASIC.FYI · Learn silicon end to end.info@asic.fyi