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Hardware interview practice

Request Exceeds Its Timeout

EasyWaveform DebuggingSystemVerilog

Each column is one rising clock edge. req and ack are one-cycle pulses, and busy marks the live pending window from request acceptance through its last allowed response edge. Rule to apply: After req rises, busy remains 1 while ack may arrive on any of the next three edges. The window closes after the third edge, so a later ack is a timeout. Which timeout assertion fails on this waveform?

Waveform for Request Exceeds Its Timeout. Signals: req, ack, busy. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. ack must arrive one to three cycles after req.
  2. B. ack must arrive exactly four cycles after req.
  3. C. req must stay high until ack arrives.
  4. D. ack must be high at the same edge as req.