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Hardware interview practice

Interpret one mixed-sign addition explicitly

MediumRTL ArithmeticSystemVerilog

For the shown 8-bit operands a = -2 and b = 3, which expression explicitly interprets both bit patterns as signed and produces the intended result 1?

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Question code

logic signed [7:0] a = -8'sd2;
logic        [7:0] b =  8'd3;
logic signed [8:0] sum;
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Answer choices

  1. A. sum = {a, b};
  2. B. sum = $signed(a) + $signed(b);
  3. C. sum = unsigned'(a + b);
  4. D. sum = a || b;
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