Q153FreeSystemVerilog
Interpret one mixed-sign addition explicitly
Interview prompt
Question
For the shown 8-bit operands a = -2 and b = 3, which expression explicitly interprets both bit patterns as signed and produces the intended result 1?
Provided context
Code to inspect
logic signed [7:0] a = -8'sd2;
logic [7:0] b = 8'd3;
logic signed [8:0] sum;Choose one
Answer choices
- A. sum = {a, b};
- B. sum = $signed(a) + $signed(b);
- C. sum = unsigned'(a + b);
- D. sum = a || b;