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Hardware interview practice

Detect duplicate valid cache tags

MediumRTL DatapathsSystemVerilog

Design a checker for a small fully associative cache set that reports whether any two valid ways contain the same tag and returns the earliest matching way pair.

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Reviewed example

Work through one case

Input
valid=4'b1111; tags by way=[A,B,A,A]
Expected output
duplicate=1; way_a=0; way_b=2

Way pairs (0,2) and (0,3) match, and the nested lowest-way priority chooses (0,2); invalid ways would not participate.

What to cover

Requirements

  1. Compare only distinct valid ways and return way_a < way_b.
  2. Ignore equal tags in invalid ways.
  3. Use lowest-way lexicographic priority when several duplicate pairs exist.
  4. Accept check only when check_ready is high, pulse done once per accepted check, and return zero indices when no duplicate exists.
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