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Hardware interview practice

Check_phase and final checking

EasyUVM ComponentsSystemVerilog

A scoreboard wants to wait in check_phase until one more actual transaction arrives. What is wrong with that plan?

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Answer choices

  1. A. Only drivers receive check_phase callbacks
  2. B. check_phase runs before build_phase and the scoreboard does not yet exist
  3. C. check_phase is a function phase and cannot consume simulation time; timed collection must finish earlier, while check_phase inspects accumulated terminal state
  4. D. check_phase automatically drains every analysis FIFO before it starts
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