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Q026FreeSystemVerilog

Four-Phase Request/Acknowledge Monitor

Difficulty
Medium
Topic
Protocol Checking
Language
SV
Interview prompt

Question

Check a four-phase handshake whose legal sequence is request rise, acknowledge rise, request fall, acknowledge fall. Data is launched with request and held until acceptance.

Starting point

Question code

class ReqAckMonitor #(int DATA_W = 32);
  void sample(bit req, bit ack, bit [DATA_W-1:0] data);
  int completed_count();
  int error_count();
endclass
Reviewed example

Trace one case

Input
cycles: (req,ack) = (0,0), (1,0), (1,1), (0,1), (0,0)
Expected output
one legal four-phase handshake; no error

The request rises before acknowledge, then request falls before acknowledge returns low.

What to cover

Requirements

  1. Reject acknowledge before request and request withdrawal before acknowledge.
  2. Require data stability from request assertion through acknowledge assertion.
  3. Do not allow a new request until both signals have returned low.
  4. Detect a timeout in each non-idle phase without repeatedly counting the same violation.
Continue practicing
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