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Hardware interview practice

Control a tiny exact-LRU associative cache

MediumRTL DesignSystemVerilog

Build a 2-to-8-way fully associative cache controller with serialized read (GET) and write/update (PUT) commands, exact least-recently-used (LRU) replacement, and a stallable one-entry response channel.

Reviewed example

Work through one case

Input
2-way empty cache: PUT A, PUT B, GET A, PUT C
Expected output
GET A hits and makes A MRU; PUT C evicts B and reports B's tag/data

After the hit, B is exact LRU; the full-cache insertion replaces only that way while A and C remain unique valid tags.

What to cover

Requirements

  1. A GET hit returns data and becomes most recently used (MRU); a GET miss leaves recency unchanged.
  2. PUT updates a hit, otherwise uses the lowest-index invalid way before evicting the exact LRU way.
  3. Keep tags unique among valid ways and report evicted tag/data only for a full-cache replacement.
  4. Hold every response field and all cache metadata stable while a response is stalled.
Continue practicing
Computer ArchitectureCompare true LRU with tree PLRU