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Q114FreeSystemVerilog

Classify timing-path startpoints and endpoints

Difficulty
Easy
Topic
Timing
Language
SV
Interview prompt

Question

A synchronous block contains primary inputs/outputs and edge-triggered registers. Which classification is correct for ordinary data paths?

Choose one

Answer choices

  1. A. A register D pin is always a startpoint and Q is always an endpoint because data flows from D to Q internally.
  2. B. Input-to-register, register-to-register, register-to-output, and input-to-output are the four basic classes; register Q and input ports can start paths, while register D and output ports can end them.
  3. C. Only register-to-register paths exist in STA; input and output delays are simulation concepts.
  4. D. Every path must start at a clock pin and end at another clock pin; data pins cannot be timing endpoints.
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