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Hardware interview practice

Grant Remains High After Request Ends

EasyWaveform DebuggingSystemVerilog

The arbiter samples req and arb_enable and drives a registered grant. arb_enable remains 1 throughout, and no request is pending after C3. Rule to apply: arb_enable=0 forces grant low. While arb_enable=1, sampling req=0 requires grant=0 after the next edge unless a new req is sampled. What is the root cause of the failure marked at C4?

Waveform for Grant Remains High After Request Ends. Signals: req, grant, arb_enable. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. grant rises one edge after req first appears.
  2. B. req is high for two cycles.
  3. C. grant is not cleared on the edge after req is sampled low.
  4. D. The arbiter is disabled at C4, so grant is not checked there.