Design verification / A field guide
From design intent
to checked behavior.
Send traffic. Break an assumption. See what the checker catches.
Can you catch a stale response?
Teaching fixture: epoch-tagged responses; reset cancels outstanding work.
Send a request to begin.
Inspect the evidence Event log & example contract
- No traffic yet. Epoch 11 is ready.
This fixture holds one current request and one old response. It carries trustworthy epoch provenance on each response. Real untagged interfaces need an agreed cancellation or drain contract; a checker cannot invent that provenance.
Reset cancels current expectations. Only a response with matching ID and epoch may retire new work. The deliberately broken ID-only mode demonstrates a false match.
Open the full reset lab ↗The case library
Start with a failure.
Pick a mechanism. Open an experiment.
13 case studies
Mid-test reset+Does old work survive reset?
Mid-Test Reset Orchestration
A driver completes a stale handshake or leaves valid asserted across reset.
Enter the lab ↗Power gating+Release isolation too early.
Power Gating, Isolation, and Retention
An output is not clamped while its source island is off.
Enter the lab ↗Clock gating+Which edge accepts the transfer?
Clock Gating and Wake-Up Integrity
The gated clock continues toggling after the IP satisfies its idle threshold.
Enter the lab ↗Ordering+A legal interleave or a violation?
Out-of-Order Ordering and Memory Consistency
A same-ID response returns in the wrong order.
Enter the lab ↗QoS & fairness+Can a busy requester starve?
QoS, Fairness, and Backpressure
A low-priority request waits beyond its allowed starvation bound.
Enter the lab ↗Negative testing+Reject the packet. Reuse its ID.
Negative Testing and Exception Scoreboarding
An expected CRC or ECC rejection appears as a false data mismatch.
Enter the lab ↗Interrupts+The tenth event—or the timeout?
IRQ Subsystem Verification
An event is dropped and the expected IRQ never arrives.
Enter the lab ↗Deadlock & livelock+No progress. What does that prove?
Deadlock, Livelock & Credit Watchdogs
Items remain in flight while the completion counter does not change for the watchdog window.
Enter the lab ↗Configurable testbenches+Can an override change an instance?
Dynamic Reconfiguration & Polymorphic Testbenches
An override is installed after creation and has no effect.
Enter the lab ↗Broadcast+Count recipients, not responses.
Broadcast Control Plane & Global TB Messaging
One or more agents miss the global event and retain stale state.
Enter the lab ↗Performance+What did the sample miss?
Performance Verification Framework
The design passes functionally but misses sustained bandwidth or latency targets.
Enter the lab ↗Clock crossings+Move the clocks. Hold the data.
CDC & RDC Dynamic Verification
Request changes again before acknowledgement and the destination loses or duplicates an event.
Enter the lab ↗Firmware ↔ hardware+What arrives at the timeout?
Firmware & Hardware-Software Interface Verification
A firmware-equivalent sequence no longer matches the current software driver or header definitions.
Enter the lab ↗Map the verification path+
One request. Two lifetimes. Six responsibilities.
Contract
Reset defines the lifetime boundary.
Start with a falsifiable claim.
A request accepted before reset must either complete in its epoch or be explicitly cancelled by the reset contract. First state what the design promises, and under which conditions.
Define risk and evidence ↗Five foundations
Choose what to learn next.
FOUNDATION / 01Verification planning↗
Turn requirements and architectural risks into features, scenarios, assertions, coverage goals, and ownership.
Tools you will use- Feature matrix
- Risk ranking
- Traceability
FOUNDATION / 02Testbench architecture↗
- 01Drive the interface↓
- 02Observe the DUT↓
- 03Predict & compare
Separate stimulus, protocol driving, observation, prediction, and checking so components can be reused and debugged independently.
Tools you will use- UVM agents
- Monitors
- Scoreboards and reference models
FOUNDATION / 03Stimulus and constraints↗
- 01Legal input space↓
- 02Boundary conditions↓
- 03Reproducible stimulus
Generate legal, meaningful traffic that reaches boundaries without hiding intent inside opaque randomization.
Tools you will use- Constrained random
- Sequences
- Scenario control
FOUNDATION / 04Assertions and formal verification↗
- 01State a property↓
- 02Check each transition↓
- 03Inspect a counterexample
State temporal contracts directly and use proofs where simulation would struggle to cover every relevant trace.
Tools you will use- SVA
- Assumptions and properties
- Bounded and unbounded proofs
FOUNDATION / 05Coverage and regression closure↗
- 01Measure the gap↓
- 02Explain its cause↓
- 03Close with evidence
Measure what was exercised, understand what was checked, triage failures, and close meaningful gaps rather than chasing percentages.
Tools you will use- Functional coverage
- Code coverage
- Regression triage
About this learning path+
Learn ASIC design verification with verification planning, SystemVerilog, UVM, assertions, formal methods, functional coverage, and regression debug.
Plan verification around risk, build reusable checking infrastructure, and know what coverage closure actually means.
Design verification builds evidence that an implementation matches its specification across normal operation, corner cases, and failure conditions. The strongest environments connect every stimulus, checker, assertion, and coverage point to a specific risk.
The engineering practice
Every check needs a reason to exist.
Start with a product risk. Build the experiment that could prove you wrong.
Start with risk and evidence ↗
Explain your decisions
Put the reasoning into practice.
What you can practice+
Prepare for UVM, scoreboards, coverage, assertions, and formal reasoning.
Build evidence, not just test traffic.+
Verification from intent to closure
Build evidence, not just test traffic.
Strong design verification ties stimulus, scoreboards, assertions, and coverage to explicit product risk. Reusable UVM infrastructure matters because it makes failures easier to reproduce, localize, and explain.
Review planning, constrained-random stimulus, reference models, formal properties, regression triage, and coverage closure as parts of one evidence system rather than isolated techniques.