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A Single Send Command Produces Two Transfers

EasyWaveform DebuggingSystemVerilog

send_one requests one output beat. The receiver is continuously ready. A transfer occurs at each edge where valid and ready are both 1. Rule to apply: Each one-cycle send_one pulse must produce exactly one transfer. After that transfer, valid must be 0 on the next edge unless a new send_one pulse occurs. Why does the receiver count two transfers?

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Waveform for A Single Send Command Produces Two Transfers. Signals: send_one, valid, ready, data. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. ready changes too late.
  2. B. valid stays high for an extra edge after the first accepted beat.
  3. C. data changes between the two transfers.
  4. D. send_one is high for two cycles.
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