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asic.fyi

Hardware interview practice

Generate and synchronize a Gray-code counter

MediumClock Domain CrossingSystemVerilog

Design a parameterized counter whose exported Gray code changes by one bit per source increment, then synchronize that Gray value into a destination clock domain.

Gray-code counter crossing from a source clock domain through a two-flop destination synchronizer, with one-bit transitions highlighted.
The Gray encoder limits adjacent count transitions to one bit; the destination synchronizer still handles metastability.
Reviewed example

Work through one case

Input
WIDTH=3; enabled source binary counts=[0,1,2,3]
Expected output
registered Gray values=[000,001,011,010]; each appears in destination after two destination edges

Each source increment changes one Gray bit, while the marked two-flop chain still handles metastability before destination use.

What to cover

Requirements

  1. Increment the binary source count by at most one on each enabled source edge.
  2. Register Gray code derived from the next binary value.
  3. Use a two-flop destination synchronizer for every Gray bit and mark the chain for CDC tools.
  4. Explain that Gray coding limits transition ambiguity but does not remove metastability or replace synchronization.
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