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Q074FreeDesign Verification

Check delayed and reordered memory writes

Difficulty
Medium
Topic
Reference Models
Language
SV
Interview prompt

Question

Compare authoritative expected memory writes with delayed or reordered DUT writes. Every expected address and data pair must receive one matching DUT write within a bounded number of cycles.

Starting point

Question code

class MemoryEventualityChecker;
  function void golden_write(longint addr, int data);
  function void dut_write(longint addr, int data);
  function void tick();
  function int error_count();
  function void end_of_test_check();
endclass
Reviewed example

Trace one case

Input
expect write (0x100,0xAA) at cycle 0 and (0x200,0xBB) at cycle 1; DUT writes them reversed at cycles 3 and 4
Expected output
both writes match; no unexpected, expired, or end-of-test entries

Matching uses address and data rather than arrival order, while both observed delays remain within the configured bound.

What to cover

Requirements

  1. Record each expected write with its arrival cycle.
  2. Match a DUT write to one unmatched expectation with the same address and data.
  3. Report unexpected DUT writes, expired expectations, and unmatched end-of-test entries.
  4. Allow matching order to differ from expected-write order.
Continue practicing
Q131 · Reference ModelsExpire memory expectations without full scansQ009 · Reference ModelsMatch out-of-order packets by IDQ178 · Reference ModelsRelease reordered responses in request order