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Hardware interview practice

Sticky Interrupt Does Not Clear

EasyWaveform DebuggingSystemVerilog

Each column is one rising clock edge. status is a sticky interrupt bit. This design registers the write-one-to-clear request, so a pulse sampled at one edge must be reflected in status at the next labeled edge. Rule to apply: If w1c is 1 and new_event is 0 at an edge, status must be 0 at the next labeled edge. A simultaneous new_event may keep status set. Which clear assertion fails on this waveform?

Waveform for Sticky Interrupt Does Not Clear. Signals: new_event, w1c, status. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. status must be 1 whenever new_event is 0.
  2. B. w1c must stay high until status is low.
  3. C. A w1c pulse without a new event must make status low on the next edge.
  4. D. new_event and w1c must always have the same value.