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Read Burst Marks the Third Beat as Last

MediumWaveform DebuggingSystemVerilog

Each column is one rising clock edge. The source sends a four-beat read burst. A beat is accepted only when valid=1 and ready=1; accepted_count is the total immediately after each edge. Rule to apply: An edge with ready=0 does not increase accepted_count. For a four-beat burst, last must be 1 only on the fourth accepted beat and must be 0 on the first three accepted beats. Which read-burst assertion fails first on this waveform?

Waveform for Read Burst Marks the Third Beat as Last. Signals: valid, ready, last, accepted_count. Numbered markers identify sampled columns.
Read the sampled columns from left to right, then test each choice against the stated timing rule.
Choose one

Answer choices

  1. A. ready must remain high on every edge of the burst.
  2. B. accepted_count must increase at C2 because valid is high.
  3. C. last must be 1 only on the fourth accepted beat, not the third beat at C5.
  4. D. valid must drop to 0 whenever ready is 0.
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