DescriptionQ069
Q069DVArchASIC interview problem
DRAM Bank Timing Checker
TechniquesDVArchDRAMTiming checkerRolling window
DifficultyHard
TopicTiming Models
LanguageSystemVerilog
Requirements5 checkpoints
01
Problem
Check a simplified dynamic random-access memory (DRAM) command stream against per-bank and global timing rules. Commands carry an explicit cycle number, bank, and row.
Type declarationSystemVerilog
typedef enum {ACT, READ, WRITE, PRECHARGE, REFRESH} dram_cmd_e;
class DramTimingChecker #(int BANKS = 16);
void observe(dram_cmd_e cmd, int bank, int row, longint cycle);
int error_count();
endclassExample input and output
Use this case to check your interpretationInput
configure tRCD=4 and tRAS=8
t=0 ACT bank0
t=2 READ bank0
t=4 READ bank0
t=7 PRE bank0
t=8 PRE bank0Output
errors at t=2 and t=7; commands at t=4 and t=8 are legalExplanation
The timing model checks elapsed cycles against both activation-to-read and minimum-active-time constraints.
02
Requirements (5)
- Track open/closed bank state and the active row in every bank.
- Enforce tRCD, tRAS, tRP, and tRC with correctly defined inclusive/exclusive boundaries.
- Enforce global ACT spacing and the four-activate window (tRRD and tFAW).
- Allow refresh only when all banks satisfy the stated precharge requirement.
- Reject nonmonotonic cycle observations and continue reporting useful diagnostics after errors.