Targeted interview collection
Broadcom-Style ASIC Interview Questions
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- Q185Eight-entry asynchronous FIFOHardCDC & RDC
- Q296Formal checker for a tagged elastic pipelineMediumAssertions & Formal
- Q341Sixteen-entry synchronous FIFOMediumRTL Design
- Q346Weighted round-robin port schedulerMediumComputer Architecture
- Q443Pause headroom at 400 Gb/sMediumComputer Architecture
- Q521Parse an Ethernet header under backpressureHardRTL Design
- Q542RoCE-style selective-repeat checkerHardSystemVerilog & UVM
- Q565Detect a transition-delay fault at speedMediumDFT & Physical Design
- Q596Validate a compact secure-boot manifestMediumFirmware & Validation
- Q601Locate the payload in an Ethernet frameEasyFirmware & Validation
- Q694Four-bit JTAG instruction registerMediumDFT & Physical Design
- Q720Decode failing SerDes lanesEasyPost-Silicon & Reliability
- Q747Subtract two PTP timestampsMediumPost-Silicon & Reliability
- Q781Ethernet low-power idle entry timerMediumLow Power
- Q871Eight-bit addition overflowEasyRTL Design
- Q940Constrain a legal Ethernet test packetEasySystemVerilog & UVM
- Q1012Scoreboard multicast switch copiesMediumSystemVerilog & UVM
- Q1021Cross a long-lived mode bitEasyCDC & RDC
- Q1041Effect of positive capture-clock skewEasyTiming & STA
- Q1061IPv4 longest-prefix-match modelHardComputer Architecture
- Q1063Calculate lane deskew tap settingsMediumTiming & STA
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